? semiconductor components industries, llc, 2002 june, 2002 rev. 12 1 publication order number: cs8361/d cs8361 5.0 v dual micropower low dropout regulator with enable and reset the cs8361 is a precision micropower dual voltage regulator with enable and reset . the 5.0 v standby output is accurate within 2% while supplying loads of 100ma and has a typical dropout voltage of 400 mv. quiescent current is low, typically 140 m a with a 300 m a load. the active reset output monitors the 5.0 v standby output and is low during powerup and regulator dropout conditions. the reset circuit includes hysteresis and is guaranteed to operate correctly with 1.0 v on the standby output. the second output tracks the 5.0 v standby output through an external adjust lead, and can supply loads of 250 ma with a typical dropout voltage of 400 mv. the logic level enable lead is used to control this tracking regulator output. both outputs are protected against overvoltage, short circuit, reverse battery and overtemperature conditions. the robustness and low quiescent current of the cs8361 makes it not only well suited for automotive microprocessor applications, but for any battery powered microprocessor applications. features ? 2 regulated outputs standby output 5.0 v 2%; 100 ma tracking output 5.0 v; 250 ma ? low dropout voltage (0.4 v at rated current) ? reset option ? enable option ? low quiescent current ? protection features independent thermal shutdown short circuit 60 v load dump reverse battery ? internally fused leads in so16l package a = assembly location wl, l = wafer lot yy, y = year ww, w = work week so16l dw suffix case 751g 1 16 reset enable 1 16 nc nc nc adj gnd gnd gnd gnd nc v trk nc nc v stby v in cs8361ydpsr7 device package shipping ordering information* cs8361ydps7 d 2 pak2 50 units/rail d 2 pak2 750 tape & reel cs8361ydwf16 cs8361ydwfr16 so16l so16l 46 units/rail 1000 tape & reel *contact your local sales representative for other package options including psop20, to220 seven lead, dip16, and so20l. 27pin. d 2 pak 7pin dps suffix case 936h 1 7 pin connections and marking diagram so16l cs8361 awlyww 1 pin 1. v stby 2. v in 3. v trk 4. gnd 5. adj 6. enable 7. reset d 2 pak cs8361 awlyyww http://onsemi.com
cs8361 http://onsemi.com 2 figure 1. block diagram. consult your local sales representative for positive enable option + v in overvoltage shutdown current limit bandgap current limit thermal shutdown + reset + gnd + ovsd tsd ovsd bg bg reset v stby 5.0 v, 100 ma, 2.0% v trk 250 ma v in adj tsd tsd ovsd v stby enable bg reset maximum ratings* rating value unit supply voltage, v in 16 to 26 v positive transient input voltage, tr > 1.0 ms 60 v negative transient invput voltage, t < 100 ms, 1.0 % duty cycle 50 v input voltage range (enable , reset ) 0.3 to 10 v tracking regulator (v trk , adj) 20 v standby regulator (v stby ) 10 v junction temperature 40 to +150 c storage temperature range 55 to +150 c esd susceptibility (human body model) 2.0 kv lead temperature soldering wave solder (through hole styles only) note 1 reflow (smd styles only) note 2 260 peak 230 peak c c 1. 10 seconds max. 2. 60 seconds max above 183 c *the maximum package power dissipation must be observed.
cs8361 http://onsemi.com 3 electrical characteristics (6.0 v v in 26 v, i out1 = i out2 = 100 m a, 40 c t a +125 c, 40 c t j +150 c; unless otherwise stated.) characteristic test conditions min typ max unit tracking output (v trk ) v trk tracking error (v stby v trk) 6.0 v v in 26 v, 100 m a i trk 250 ma. note 3 25 +25 mv adjust pin current, i adj loop in regulation 1.5 5.0 m a line regulation 6.0 v v in 26 v. note 3 5.0 50 mv load regulation 100 m a i trk 250 ma. note 3 5.0 50 mv dropout voltage (v in v trk ) i trk = 100 m a. i trk = 250 ma 100 400 150 700 mv mv current limit v in = 12 v, v trk = 4.5 v 275 500 ma quiescent current v in = 12 v, i trk = 250 ma, no load on v stby 25 50 ma reverse current v trk = 5.0 v, v in = 0 v 200 1500 m a ripple rejection f = 120 hz, i trk = 250 ma, 7.0 v v in 17 v 60 70 db standby output (v stby ) output voltage, v stby 6.0 v v in 26 v, 100 m a i stby 100 ma. 4.9 5.0 5.1 v line regulation 6.0 v v in 26 v. 5.0 50 mv load regulation 100 m a i stby 100 ma. 5.0 50 mv dropout voltage (v in v stby ) i stby = 100 m a. i stby = 100 ma 100 400 150 600 mv mv current limit v in = 12 v, v stby = 4.5 v 125 200 ma short circuit current v in = 12 v, v stby = 0 v 10 100 ma quiescent current v in = 12 v, i stby = 100 ma, i trk = 0 ma v in = 12 v, i stby = 300 m a, i trk = 0 ma 10 140 20 200 ma m a reverse current v stby = 5.0 v, v in = 0 v 100 200 m a ripple rejection f = 120 hz, i stby = 100 ma, 7.0 v v in 17 v 60 70 db reset enable functions enable input threshold 0.8 1.2 2.0 v enable input bias current v enable = 0 v to 10 v 10 0 10 m a reset threshold high (v rh ) v stby increasing 4.59 4.87 v stby 0.02 v reset hysteresis 60 120 180 mv reset threshold low (v rl ) v stby decreasing 4.53 4.75 v stby 0.08 v reset leakage 25 m a output voltage, low (v rlo ) 1.0 v v stby v rl , r rst = 10 k w 0.1 0.4 v output voltage, low (v rpeak ) v stby , power up, power down 0.6 1.0 v protection circuitry (both outputs) independent thermal shutdown v stby v trk 150 150 180 165 c c overvoltage shutdown 30 34 38 v 3. v trk connected to adj lead. v trk can be set to higher values by using an external resistor divider.
cs8361 http://onsemi.com 4 package pin description package pin # d 2 pak, 7 pin so16l pin symbol function 1 16 v stby standby output voltage delivering 100 ma. 2 1 v in input voltage. 3 3 v trk tracking output voltage controlled by enable delivering 250 ma. 4 4, 5, 12, 13 gnd reference ground connection. 5 6 adj resistor divider from v trk to adj. sets the output voltage on v trk . if tied to v trk , v trk will track v stby . 6 8 enable provides on/off control of the tracking output, active low. 7 9 reset cmos compatible output lead that goes low whenever v stby falls out of regulation. 2, 7, 10, 11, 14, 15 nc no connection. circuit description enable function the enable function switches the output transistor for v trk on and off. when the enable lead voltage exceeds 1.4 v (typ), v trk turns off. this input has several hundred millivolts of hysteresis to prevent spurious output activity during powerup or powerdown. reset function the reset is an open collector npn transistor, controlled by a low voltage detection circuit sensing the v stby (5.0 v) output voltage. this circuit guarantees the reset output stays below 1.0 v (0.1 v typ) when v stby is as low as 1.0 v to ensure reliable operation of microprocessor based systems. v trk output voltage this output uses the same type of output device as v stby , but is rated for 250 ma. the output is configured as a tracking regulator of the standby output. by using the standby output as a voltage reference, giving the user an external programming lead (adj lead), output voltages from 5.0 v to 20 v are easily realized. the programming is done with a simple resistor divider (figure 2), and following the formula: v trk v stby (1 r1 r2) i adj r1 if another 5.0 v output is needed, simply connect the adj lead to the v trk output lead. c1* 0.1 m f gnd cs8361 mcu b+ v in v trk adj enable reset v stby r3 v dd c2** 10 m f esr < 8.0 w 5.0 v, 100 ma reset i/o r2 r1 c3** 10 m f esr < 8.0 w sw 8.0 v, 250 ma gnd v trk ~ v stby (1 + r1/r2) for v trk ~ 8.0 v, r1/r2 ~ 0.6 *c1 is required if regulator is located far from power supply filter. **c2 and c3 are required for stability. figure 2. test and application circuit, 5.0 v, 8.0 v regulator
cs8361 http://onsemi.com 5 c1* 0.1 m f gnd cs8361 mcu b+ v in v trk adj enable reset v stby r3 v dd c2** 10 m f esr < 8.0 w 5.0 v, 100 ma reset i/o c3** 10 m f esr < 8.0 w sw 5.0 v, 250 ma gnd *c1 is required if regulator is located far from power supply filter. **c2 and c3 are required for stability. figure 3. test and application circuit, dual 5.0 v regulator application notes external capacitors output capacitors for the cs8361 are required for stability. without them, the regulator outputs will oscillate. actual size and type may vary depending upon the application load and temperature range. capacitor effective series resistance (esr) is also a factor in the ic stability. worstcase is determined at the minimum ambient temperature and maximum load expected. output capacitors can be increased in size to any desired value above the minimum. one possible purpose of this would be to maintain the output voltages during brief conditions of negative input transients that might be characteristic of a particular system. capacitors must also be rated at all ambient temperatures expected in the system. to maintain regulator stability down to 40 c, capacitors rated at that temperature must be used. more information on capacitor selection for smart regulator ? s is available in the smart regulator application note, acompensation for linear regulators,o document number sr003an/d, available through the literature distribution center or via our website at http://www.onsemi.com. calculating power dissipation in a dual output linear regulator the maximum power dissipation for a dual output regulator (figure 4) is p d(max) v in(max) v out1(min) i out1(max) v in(max) v out2(min) i out2(max) v in(max) iq (1) where: v in(max) is the maximum input voltage, v out1(min) is the minimum output voltage from v out1 , v out2(min) is the minimum output voltage from v out2 , i out1(max) is the maximum output current, for the application, i out2(max) is the maximum output current, for the application, and i q is the quiescent current the regulator consumes at both i out1(max) and i out2(max) . once the value of p d(max) is known, the maximum permissible value of r q ja can be calculated: r ja 150 c t a p d (2) the value of r q ja can be compared with those in the package section of the data sheet. those packages with r q ja 's less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. figure 4. dual output regulator with key performance parameters labeled. smart regulator control features v out1 i out1 v out2 i out2 v in i in i q heat sinks a heat sink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air.
cs8361 http://onsemi.com 6 each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r q ja : r ja r jc r cs r sa (3) where: r q jc = the junctiontocase thermal resistance, r q cs = the casetoheatsink thermal resistance, and r q sa = the heatsinktoambient thermal resistance. r q jc appears in the package section of the data sheet. like r q ja , it too is a function of package type. r q cs and r q sa are functions of the package type, heatsink and the interface between them. these values appear in heat sink data sheets of heat sink manufacturers.
cs8361 http://onsemi.com 7 package dimensions so16l dwf suffix case 751g03 issue b d 14x b 16x seating plane s a m 0.25 b s t 16 9 8 1 h x 45 m b m 0.25 h 8x e b a e t a1 a l c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not inlcude mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 10.15 10.45 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7 d 2 pak 7pin dps suffix case 936h01 issue o t dim min max min max millimeters inches a 0.326 0.336 8.28 8.53 b 0.396 0.406 10.05 10.31 c 0.170 0.180 4.31 4.57 d 0.026 0.036 0.66 0.91 e 0.045 0.055 1.14 1.40 f 0.058 0.078 1.41 1.98 g 0.050 bsc 1.27 bsc h 0.100 0.110 2.54 2.79 j 0.018 0.025 0.46 0.64 k 0.204 0.214 5.18 5.44 m 0.055 0.066 1.40 1.68 n 0.000 0.004 0.00 0.10 notes: 1. dimensions and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. tab contour optional within dimensions b and m. 4. dimensions a and b do not include mold flash or gate protrusions. mold flash and gate protrusions not to exceed 0.025 (0.635) max. b n a k m e c seating plane f h j d 7 pl g t m 0.13 (0.005) m b 12345 u 0.256 ref 6.50 ref v 0.305 ref 7.75 ref 67 8 u v
cs8361 http://onsemi.com 8 package thermal data parameter so16l d 2 pak, 7pin unit r q jc typical 18 3.5 c/w r q ja typical 75 1050* c/w *depending on thermal properties of substrate. r q ja = r q jc + r q ca . on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. cs8361/d smart regulator is a registered trademark of semiconductor components industries, llc (scillic). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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